A typical current mirror circuitry 10, which can be found in textbooks on microelectronics, is shown in FIG. 1a (see, e.g. "Microelectronics Circuits" by Adel S. Sedra and Kenneth C. Smith, Oxford University Press, 1991, pp. 428-435). This current mirror is known to be sensitive to parasitic resistances caused by interconnections between a transistor and other circuit elements as illustrated by dotted boxes in FIG. la at interconnection points "a", "b", "c" and "d". It means that minor variations of parasitic resistances result in exponential changes of the output current, which might be unacceptable in many practical situations. As an improvement to FIG. 1a, another prior art current mirror circuit 20, shown in FIG. 1b, includes regeneration resistors R.sub.1i, R.sub.1o, R.sub.2i, and R.sub.2o at corresponding interconnection points. As a result, the improved current mirror becomes substantially less sensitive to parasitic resistances due to the fact that regeneration resistances are much greater than parasitic resistances and therefore provide much less relative variations of the magnitude of the combined resistances.
However, introduction of regeneration resistors, while solving the above-mentioned circuit sensitivity problem, introduces another inherent problem of having a differential current offset caused by a mismatched layout of regeneration resistors. It means that the output differential current offset exists even though all the transistors are matched and differential current at the input of the current mirror is zero. Accordingly, there is a need to design a current mirror circuitry which would provide reduced or no differential current offset while maintaining other qualities of the circuitry.